Windows系统下(Linux和MAC系统下请自行了解清楚)NI的各种软件、模块、工具包、驱动程序,使用NI许可证管理器来激活的,绝大部分的都可以使用NI Lincense Activator来激活:NI序列号Serial Number生成激活工具NI License Activator,LabVIEW/VBAI/VDM/VAS等软件模块工具包破解工具不限版本http://pcmv.cn/thread-490-1-1.html
视觉论坛的各种NI资源,除了视觉相关的模块有使用外,大部分的都不会使用,仅提供资源不提供技术支持。资源的下载地址一般会同时提供NI官方和百度网盘的地址。某些工具包NI地址失效或没有NI地址,只能使用百度网盘地址;如果百度网盘地址失效过期,可联系论坛客服更新。NI的服务器在美国,有时候速度很慢或下载容易出错,这样会造成安装时各种错误而无法安装。建议在下载完成后,对下载资源做校验和(NI一般会提供MD5或SHA256等)验证,与官方或视觉论坛提供的校验和对比,一致就可以安装;如不一致,则需要重新下载。视觉论坛早期下载上传的资源,基本上都是正常下载的资源;2019后下载的资源,都与NI的正确校验和对比过,保证是正确的资源才上传到百度网盘。校验和工具下载地址:文件Hash计算器FHash,文件校验和验证下载文件正确性验证,MD5值计算、SHA1值计算、SHA256值计算、CRC32值计算http://pcmv.cn/thread-26524-1-1.html
NI Circuit Design Suite 14.0 Pro Win32Eng/Ger NI电路设计套件14.0专业版
Circuit Design Suite(CDS)电路设计套件
电路设计套件结合了Multisim和Ultiboard软件,为电路设计、仿真、验证和布局提供了一套完整的工具。
电路设计套件为您提供了直观且经济高效的设计电路工具。您可以执行交互式SPICE仿真并无缝转换到PCB布局和布线软件。该套件专为教学、科研和设计而开发,提供了先进的仿真功能,可以让您清楚地了解电路在各种场景下的性能。
14.0Pro
zip
文件大小: 716561237 字节 (683.37 MB)
修改日期: 2019-06-25 02:41
MD5: 46ee74f1db1a5066e53432619eff0197(官方正确)
SHA1: 9e65781337e08b64ce4ded6ca7608e4ef8251035
SHA256: 47a8330cae50a86e5b31525ef1e05f014807d5aa0e8441824ee3f9d133be144f
CRC32: c7629a8f
exe
文件大小: 717312856 字节 (684.08 MB)
修改日期: 2015-03-27 10:23
MD5: c3fb4f9699b65ee7fb817a421d60c20d
SHA1: cd295c0ea3015b94f1c36b8534168d7a8e239c49
SHA256: 5bd697f15e14f97b9323e223640670b980e6f48dd7eec58ca77a11bb507e272e
CRC32: 443b849d
百度网盘与NI官方下载地址:
NI Circuit Design Suite 14.0 Pro Win32Eng/Ger NI电路设计套件14.0专业版
http://pcmv.cn/thread-26719-1-1.html?fromuid=9
(出处: 机器视觉论坛)
NI Circuit Design Suite 14.0 Readme for Windows
Supported Platforms
Windows 8.1/8/7/Vista (32-bit and 64-bit).
Windows XP SP3 (32-bit).
Windows Server 2008 R2 (64-bit).
Windows Server 2003 R2 (32-bit).
Pentium 4/M class microprocessor or equivalent.
512 MB of memory (256 MB minimum).
2 GB of free hard disk space.
1024 x 768 screen resolution.
To develop custom LabVIEW-based instruments for use in Multisim, LabVIEW 2013 or 2014 is required.
NI Circuit Design Suite Drops Support for Microsoft Windows Vista, Windows XP, and Windows Server 2003 in 2016
Installing Circuit Design Suite 14.0Installing Multiple Versions
Archiving Circuit Design Suite databases
Uninstalling
Circuit Design Suite 14.0 Updates and Notifications
Automating the Installation of NI Products
For more information on silent installations of individual NI products, refer to KB 4CJDP38M, Automating the Installation of a Single Installer.
For more information on silent installations of suited NI products, such as NI Developer Suite, refer to KB 4GGGDQH0, Automating the Installation of a Suited Installer.
To determine what version of NI Installers your product contains, refer to KB 4CJDR18M, How Can I Determine the Type and Version of My National Instruments Installer?.
How to Use NI Software with Microsoft Windows 8.x
Using NI Launcher
Pinning Frequently Used Applications
Current Application | Icon Location | Pin to Action |
Windows 8 Desktop | Desktop Taskbar | Right-click application and select Pin to Taskbar |
Windows 8 Desktop | Start screen | Right-click application and select Pin to Start |
Windows 8 Start screen | Desktop Taskbar | Right-click application and select Pin to taskbar from the menu bar on the bottom of the screen |
Finding All Programs
Product Security and Critical Updates
Known IssuesLabVIEW
Windows Vista
Circuit Design Suite
Bug Fixes
Multisim ( 61 ) | |
Bug ID | Description |
518929 | Update components sometimes do not detect ELVISmx instruments components from an ELVIS schematic. |
517825 | Pasting a Title Block will not preserve the field values on multi-page sheet. |
514757 | Net names with special internal character $ is being allowed to be created, which may cause issues with the netlist. |
515526 | Importing a .cir file sometimes causes Multisim to crash. |
501065 | Schematic wires sometimes may appear as connected but in reality are not. |
509888 | Imported files can sometimes show a component's database location incorrectly. |
479149 | Unable to change the value for a RLC custom part. |
465428 | Setting a component value visible will sometimes place the RefDes away from the schematic symbol. |
490625 | Single pin source changes do not create an undo point. |
491624 | Modifying values on single pin sources, the SPICE netlist viewer does not get its "out of date" message. |
511469 | Multisim sometimes does not display correctly a component's value compared to the actual value. |
466171 | Component Wizard fails to provide all model nodes when line continuations are separated by comment lines. |
506416 | Replacing some components by hierarchical block or subcircuit within an hierarchical block will sometimes crash Multisim. |
504931 | Default digital graph color is difficult to see with default background. |
274344 | Editing a component in database should modify and not create a new component. |
493395 | SPICE model type is no longer shown in table view for basic RLC device models. |
491327 | Undo sometimes causes inconsistency between netlist and shematic. |
503533 | Multisim hangs when scope with normal trigger and non-default trigger value is used. |
500035 | Cannot use exponential number format in probe parameter values. |
368543 | Cannot save analysis settings without specifying output variables. |
465372 | The LVM source generates incorrect negative polarity signal. |
274752 | Oscillopscope's AC coupling generates a poor result. |
479847 | Uninstalling 13.0.1 causes an error message next time 12.0.1 is started. |
396771 | Checking for current sources in series will only check the first two nodes of objects defined in the netlist. |
282395 | Attribute Device incorrectly repeats attribute Value in non-RLC components. |
367605 | Adding a new bus line should use net name as its default bus line name. |
461943 | Non-ideal resistor doesn't behave correctly without brackets around its model expression. |
473601 | Using Update Components should report any broken connections. |
487152 | When adding device parameters to analysis setup, unwanted parameters are also added. |
478607 | Cmod S6 config files are missing internal clock pins. |
490907 | Renaming a DGND component will not update other DGND instances. |
440051 | Malconfigured pulse source causes an internal error during simulation. |
485982 | Hierarchical PLD design sometimes prompts for net name collision continuosly. |
488395 | Exponential voltage/current source has different behaviour than in PSPICE. |
485448 | Octave AC sweep disregards logarithmic y axis. |
486102 | Error mesasge is not clear when simulating with an expression that evaluates a divided by zero value. |
403700 | LabVIEW microphone instrument is not able to acquire data for more than 10 sec. |
274615 | Multisim sometimes shows a white screen for a period of time while opening a file. |
424840 | Component Wizard allows different number of symbol pins in ANSI vs IEC. |
467540 | Some frequency-domain analyses display seconds as the unit in the simulation status bar. |
323705 | DMM uses 1e-9ohm series resistor to measure current, which causes convergence issues. |
394799 | Unable to set the Xilinx path in Multisim for all users using the same computer. |
443707 | Fourier analysis doesn't display DC component in graph. |
393295 | Grapher does not appear to handle very small values well and rounds them off to zero. |
462216 | The grapher's Y-axis marks do not match up with trace values. |
480780 | AC Phase confined to and jumps between -180 and 180. |
478305 | RefDes and Value are 'top aligned' when part is rotated in the vertical position. |
269360 | Pole-zero analysis does not remember the analysis type setting. |
465765 | Vertical symbol text renders horizontally when placed on schematic. |
472570 | Triangular current source seems to only reach the peak current on the first period. |
469208 | Unable to assign a footprint to a component with no footprints, assignment from the spreadsheet no longer works. |
195405 | No clean way of stopping Wait for Next Output in Multisim COM API. |
466133 | Logic Converter sometimes crashes when converting an expression to logic circuit. |
465748 | Simulation slows down after changing parameters on the Function Generator. |
465038 | Certain symbols from master database are reported as invalid when saving to user database. |
347561 | The Schematic Statistic Report incorrectly counts each section of a multi-section component as a part. |
456597 | Components with unmapped model nodes can be saved to database from the model template view without warning. |
274318 | Placing a component with a user-created footprint will reset it to a default footprint. |
456610 | Adding a section to a component with custom section names doesn't map all pins. |
458840 | Copy and paste components to a new design will re-enumerate its refdeses. |
459432 | PLD components not flagged correctly after saving to database. |
Ultiboard ( 40 ) | |
Bug ID | Description |
470546 | Importing a DXF file sometimes does not draw the pads correctly. |
507801 | Ultiboard sometimes places annotated components on top of existing components. |
512407 | Moving a part around a group of parts object will cause to crash Ultiboard. |
480776 | Toggling layer visibility for copper stack up layers with micro via placed on them may lead to Multisim crash. |
268382 | Autorouting of buses should not have vertical trace segments. |
275699 | Ultiroute incorrectly runs traces over a custom pad shape. |
444411 | Non-standard fill styles do not work on copper areas that are not power planes. |
495370 | Ultiboard crashes when follow-me router is used after changing clearance. |
274648 | Rule precision should not round to significant digits. |
320661 | The unit dropdown in Global options >> PCB design does not seem to get affected when units are changed from main toolbar control. |
266630 | Fanout SMD does not work well in BGA packages. |
264328 | Follow me router violates DRC when auto narrow traces is enabled. |
275664 | Trace running over a via without copper ring doesn't cause connectivity error. |
387633 | Duplicate footprint is added to the PCB when a footprint without pin is forward annotated. |
443579 | Fiducial marks are located incorrectly when text attribute is used outside the board outline. |
445863 | Text attribute voiding uses larger boundary box when attribute is rotated. |
450179 | When parts are set to transparent, one can no longer see through parts in 3D view |
286414 | NC Drill export generates incorrect file due to some decimal points in the coordinate area of the drill. |
362253 | Attempting to change the RefDes visibility for multiple components will prompt an error message and will still allow to proceed. |
440295 | Through-hole pad properties window is missing rounded rectangle as an option. |
351243 | Ultiboard does not show properly when there is a μ in the component's value tag. |
445866 | Soldermask option in via only allows none or all of the via covered. |
284242 | Placing a hole does not have a soldermask on the hole by default. |
467306 | Ultiboard database browser failing to refresh preview and place the selected part. |
275527 | Net shielding field in Net Edit dialog looses focus during edit. |
290268 | Cannot add a vertex by simply right clicking on the vertex. |
461581 | Ultiboard's grab-and-drag layout behaviour is different than Multisim. |
263206 | Import from Protel sometimes loses via connection. |
274339 | Grouped components edited via spreadsheet do not undo correctly. |
274629 | Cannot ungroup multiple group objects at once. |
276402 | Using the delete Open Trace Ends tool sometimes removes complete connections. |
274708 | Unknown footprint is sometimes ignored when importing from an older netlist. |
324536 | Test point sometimes generates an invalid DRC message. |
346268 | Changing a value in the spreadsheet view sometimes does not update the DRC result tab. |
269514 | Incorrect pad radius will generate error message when ultiroute is run. |
275732 | False DRC errors created when placing a net bridge underneath a component. |
278859 | When replacing a footprint on the design, text attributes sometimes changes unexpectedly. |
272973 | Router sometimes will not start due to an object in the silkscreen layer. |
420397 | Cancelling the Gerber-D Import dialog will prompt a invalid warning message. |
420320 | Net bridges do not export properly to DXF. |
New Components
Important InformationCopyright
Notices are located in the <National Instruments>_Legal Information and <National Instruments> directories.
EULAs are located in the <National Instruments>SharedMDFLegallicense directory.
Review <National Instruments>_Legal Information.txt for information on including legal information in installers built with NI products.