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NI Circuit Design Suite 12.0 Edu Beta Win32Eng/Ger/Jpn NI电路设计套件12.0教学版Beta版
Circuit Design Suite(CDS)电路设计套件
电路设计套件结合了Multisim和Ultiboard软件,为电路设计、仿真、验证和布局提供了一套完整的工具。
电路设计套件为您提供了直观且经济高效的设计电路工具。您可以执行交互式SPICE仿真并无缝转换到PCB布局和布线软件。该套件专为教学、科研和设计而开发,提供了先进的仿真功能,可以让您清楚地了解电路在各种场景下的性能。
12.0EDU Beta
文件大小: 575470264 字节 (548.81 MB)
修改日期: 2011-10-13 03:58
MD5: 8fedd04fb99c635e23d5940fd7be9054
SHA1: 92ce41d44c74d2b28f99b4250b1a33652663beee
SHA256: de12156146b9733fc70bf9eb6682f880342e20ca67ccf02ed158a0bf3f21a111
CRC32: efe80d13
百度网盘与NI官方下载地址:
NI Circuit Design Suite 12.0 Edu Beta Win32Eng/Ger/Jpn NI电路设计套件12.0教学版Beta版
http://pcmv.cn/thread-26705-1-1.html?fromuid=9
(出处: 机器视觉论坛)
NI Circuit Design Suite 12.0 Beta Readme for Windows
Supported Platforms
Installing Circuit Design Suite 12.0 BetaInstalling Multiple Versions
Installing Circuit Design Suite Silently
Archiving Circuit Design Suite databases
Uninstalling
Known IssuesLabVIEW
LabVIEW functionality (LabVIEW instruments and grapher interpolation) will not work if the installation path uses characters that are not native to the "Language for non-Unicode programs" setting, available by selecting Start»Control Panel»Regional and Language Options and selecting the Advanced tab. In the Vista OS, use the "Current language for non-Unicode programs:" setting in the Administrative tab. LabVIEW functionality works for Unicode characters that are native to this setting.
Windows Vista
You cannot install Circuit Design Suite 12.0 Beta on Windows Vista Starter edition.
Circuit Design Suite
Multisim and Ultiboard leak GDI resource handles when used over extended periods of time, eventually leading to unpredictable user interface behavior and crashes. This is an issue with MFC applications running on Windows XP SP2 and Windows Server 2003. For more information and workarounds, refer to KB 4JREGSXL:Multisim or Ultiboard Leaking GDI Resource Handles.
Bug Fixes
Multisim ( 41 ) | |
Bug ID | Description |
265284 | Breadboard wire color dialog not initialized properly after saving a file. |
265615 | When an MCU within a Hierarchical Block is replaced by a subcircuit, the circuit cannot be simulated. |
265831 | Multi section component model mapping does not copy to the other sections in some cases. |
265950 | Schematic read-only option allows modifying the schematic in some cases. |
268734 | TRIAC Models do not simulate as expected. |
269201 | PZT2907A and PZT2907A should be PNP components. |
271671 | .IC and .NODESET commands malfunction if used within .subckt. |
272323 | Creating a MCU project using external hex does not enable finish until the radio is explicitly clicked. |
273706 | Naming two or more nodes of a subcircuit with the same name should generate an error. |
273796 | Unable to rename a RefDes' second character to a capital letter if it is small caps. |
273824 | Local refdes of connector is not allowed to be used by a component as an "instance" refdes. |
273957 | The default prefix for a switch should be S instead of J. |
274023 | Gate optimizer does not work for components with custom section names. |
274179 | Changing case of refdes can cause trouble with placing multi-section components. |
274359 | Deleting wire segment clears perferred net name in some cases. |
274388 | User database template should have more intuitive name. |
274418 | A part with a family name that has a space causes simulation errors. |
274472 | Clicking the mouse wheel should pan the document in Multisim. |
274501 | Replace by subcircuit action on multisection components can change their Refdes in some cases. |
274508 | Replace by subcircuit of existing subcircuit causes invalid refdes entries to be added for new subcircuit in some cases. |
274656 | Updating Circuit Components resets RefDes across subcircuits. |
274869 | Unable to hide the SC symbol name for a bus connector via sheet properties. |
275479 | X is not placed on common pin of multisection component that is connected to a net after running a gate optimize operation. |
275491 | Shorting Bus Lines causes crash in some cases. |
275519 | MCU source file in hierarchical block removed in Design Toolbox does not get removed in different instance and causes crash. |
275616 | Bus Vector Connect dialog not filled in when first opened. |
275691 | Potentiometer Not Displaying Increment Precision Digits. |
283843 | BOM Report to Text is incorrect if the order of the columns is modified. |
285414 | PWL source with Unicode characters in the path fails to simulate. |
287439 | 1N5619GP diode uses the incorrect simulation model. |
289548 | JK flip flop in a PLD design does not work as expected. |
291144 | Duplicate pages show up in a multi-page design when you add it to a project. |
291724 | Multisim Crashed when non convergent analyses are swept in some cases. |
306485 | Naming and modifying nets across different instances of a subcircuit can cause Multisim to crash. |
307199 | Using the digital state machine with a very long file name will cause a crash. |
307472 | Undo does not undo the bus color change. |
310422 | A Hierarchical block connector on a multi-page design is not renamed correctly in some cases. |
310826 | Cancelling the placement of a HB from file will affect the netlist for the opened design. |
311328 | Multisim crashes when copying a HB that contains a missing HB. |
312095 | Transfer to Ultiboard of Large Design causes Ultiboard to become unresponsive. |
315461 | AD8694* components have incorrect footprint pin mappings. |
Ultiboard ( 25 ) | |
263374 | Importing an Orcad max file will make the component refdes a part of the footprint's name. |
263473 | Clearance for elliptical arc drawn improperly. |
263501 | Active layer should determines which component are selected when components are on both side. |
268476 | Two vias on top of each other does not cause a DRC error. |
268559 | Gerber import doesn't draw lines with square arperture definitions correctly. |
269497 | Unable to export a real circle to DXF. |
269525 | Save All menu option does not work in Footprint Edit mode. |
270367 | Elliptical Arc clearance isn't displayed until arc is completed. |
270512 | Copper area outside the board outline is not removed. |
270534 | Coordinates doesn't appear after exiting from the 3D viewer. |
271327 | "Convert Closed Objects To Filled" Is Not Working in some cases. |
271508 | Change shape command can cause DRC errors and broken boards. |
273482 | Keep in/Keep out polygons should have polygon list accessible to user. |
273492 | Keep in/Keep out areas abutting two sides of a board outline causes nonexistant DRC error with power plane. |
273785 | Unable to change the clearance of a net bridge. |
274247 | Searching does not find results when in in-place part edit. |
274312 | A locked rectangle does not show the locked orange border. |
274324 | Placed net bridge has a value of ?. |
274325 | Replace part is replacing a netbridge with a normal PCB part. |
274378 | Saving default layers for a design that has imported layers saves custom layers that cannot be later removed. |
274609 | Moving land patterns from one database to another doesn't actually delete the data from the source database. |
287628 | The netbridge trace shorts with copper area in some cases. |
291652 | Passwords do not protect user/coorporate databases in Ultiboard. |
299398 | Undoing an action that added layers does not remove the layers. |
308758 | Switching trace layers causes Ultiboard to crash in some cases. |
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